Integrated circuits often include analog circuits for supporting radio-frequency (RF) operation. Analog circuits operating at such high frequencies are typically sensitive to parasitic components such as parasitic resistive components and capacitive components (sometimes referred to collectively as “RC” components), whose values may vary depending on how the analog circuits are physically laid out on the integrated circuit die.
As an example, it is generally desirable to arrange the components in a symmetrical or systematic configuration to help minimize possible mismatches or mitigate other random processing effects. As another example, it is generally desirable to place two connected circuits close to each other to minimize the propagation delay between them. In general, it is important to avoid costly layout iterations for the RF/analog circuit design on more advanced process technology nodes since additional iterations slow down the design process and drive up cost.
One way to reduce the number of iterations is to provide resistive-capacitive (RC) design targets for the circuit layout designer to meet when drawing the layout so that the post layout design will still meet the overall RF design specifications. However, conventional methods for identifying accurate RC design targets is a rather manual as well as laborious task for the circuit designer. Quick prototyping tools have been developed that enable layout designers to quickly evaluate their layout design to see if it violates the circuit designer's RF design specifications. The layout designer, however, rarely has the experience of know-how to translate the RF design specifications such as gain-bandwidth (GBW), slew rate, or jitter into RC design targets.
It is within this context that the embodiments described herein arise.